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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr20m1170 i2c/spi uart with 64-byte fifo july 2012 rev. 1.1.0 general description the xr20m1170 1 (m1170) is a high performance universal asynchronous receiver and transmitter (uart) with 64 byte tx and rx fifos and a selectable i 2 c/spi slave interface. the m1170 operates from 1.62 to 3.63 volts. the enhanced features in the m1170 include a programmable fractional baud rate generator, an 8x and 4x sampling rate that allows for a maximum baud rate of 16 mbps at 3.3v. the standard features include 16 selectable tx and rx fifo trigger levels, automatic hardware (rts/cts) and software (xon/xoff) flow control, and a complete modem interface. onboard registers provide the user with operational status and data error flags. an inte rnal loopback capability allows system diagnostics. the m1170 is available in the 24-pin qfn, 16-pin qfn, 24-pin tssop and 16- pin tssop packages. n ote : 1 covered by u.s. patent #5,649,122 applications ? portable appliances ? battery-operated devices ? cellular data devices ? factory automation and process controls features ? 1.62 to 3.6 volt operation ? selectable i 2 c/spi interface ? spi clock frequency up to 18 mhz at 3.3 v 16 mhz at 2.5 v 8 mhz at 1.8 v ? full-featured uart data rate of up to 16 mbps at 3.3 v data rate of up to 12.5 mbps at 2.5 v data rate of up to 8 mbps at 1.8 v fractional baud rate generator transmit and receive fifos of 64 bytes 16 selectable tx and rx fifo trigger levels automatic hardware (rts/cts) flow control automatic software (xon/xoff) flow control halt and resume transmission control automatic rs-485 ha lf-duplex direction control output via rts# wireless infrared (irda 1.0 and 1.1) encoder/ decoder automatic sleep mode (< 15 ua at 3.3v) general purpose i/os full modem interface ? crystal oscillator (up to 24mhz) or external clock (up to 64mhz) input ? 24-qfn, 16-qfn, 24-tssop, 16-tssop packages f igure 1. xr20m1170 b lock d iagram i 2 c/spi interface i2c/spi# so a1/si a0/cs# scl sda irq# crystal osc/buffer brg uart regs xtal2 xtal1 64 byte tx fifo gpios tx rx cts# rts# gpio[7:0] 1.62v ? 3.63v vcc 64 byte rx fifo
f igure 2. p in o ut a ssignment 24-pin tssop 3 5 4 7 6 8 9 10 11 12 1 2 13 14 15 16 17 18 19 20 21 22 23 24 vcc a0/cs# a1/si so gpio0 gpio1 i2c/spi# rx tx gpio2 xtal1 xtal2 gpio7/ri# gpio6/cd# cts# reset# gpio4/dsr# gpio5/dtr# rts# irq# scl sda gnd gpio3 16-pin tssop 3 5 4 7 6 8 1 2 a0/cs# a1/si so i2c/spi# rx tx xtal1 xtal2 9 10 11 12 13 14 15 16 vcc cts# reset# rts# irq# scl sda gnd 24-pin qfn 123456 gpio1 i2c/spi# rx tx gpio0 so 11 12 7 10 8 9 xtal2 gpio3 gnd sda xtal1 gpio2 18 17 16 15 14 13 20 19 24 21 23 22 vcc gpio7/ri# gpio6/cd# cts# a0/cs# a1/si gpio5/dtr# rts# irq# scl gpio4/dsr# reset# 16-pin qfn 1234 rx tx i2c/spi# so 5 8 6 7 gnd sda xtal2 xtal1 12 11 10 9 16 13 15 14 vcc cts# a0/cs# a1/si irq# scl rts# reset# ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr20m1170il24-f 24-pin qfn -40c to +85c active xr20m1170il24tr-f 24-pin qfn -40c to +85c active xr20m1170il16-f 16-pin qfn -40c to +85c active XR20M1170IL16TR-F 16-pin qfn -40c to +85c active xr20m1170ig24-f 24-lead tssop -40c to +85c active xr20m1170ig24tr-f 24-lead tssop -40c to +85c active xr20m1170ig16-f 16-lead tssop -40c to +85c active xr20m1170ig16tr-f 16-lead tssop -40c to +85c active xr20m1170 2 i2c/spi uart with 64-byte fifo rev. 1.1.0 n ote : tr = tape and reel, f = green / rohs
xr20m1170 3 rev. 1.1.0 i2c/spi uart with 64-byte fifo pin descriptions pin description n ame 24-qfn p in # 16-qfn p in # 24-tssop p in # 16-tssop p in # t ype d escription i2c (spi) interface gpio0 2 - 5 - i/o general purpose i/o pin. gpio1 3 - 6 - i/o general purpose i/o pin. i2c/spi# 4 2 7 4 i/o i 2 c-bus or spi interface select. i 2 c-bus interface is selected if this pin is high. spi interface is selected if this pin is low rx 5 3 8 5 i uart receive data or infrared receive data. uart receive data input must idle high. infrared receive data input must idle low. if this pin is not used, tie it to vcc or pull it high via a 100k ohm resistor. tx 6 4 9 6 o uart transmit data or infrared encoder data. in the standard uart transmit data mode, the tx signal will be high during reset or idle (no data). in the infrared mode, the inactive state (no data) for the infrared encoder/decoder interface is low. if ithis pin is not used, it should be left unconnected. gpio2 7 - 10 - i/o general purpose i/o pin. xtal1 8 5 11 7 i crystal or external clock input. xtal2 9 6 12 8 o crystal or buffered clock output. gpio3 10 - 13 - i/o general purpose i/o pin. gnd 11 7 14 9 pwr power supply common, ground. sda 12 8 15 10 o i 2 c-bus data input/output (open-drain). if spi con - figuration is selected, then this pin is undefined and must be connected to vcc. scl 13 9 16 11 i i 2 c-bus or spi serial input clock. when the i 2 c-bus interface is se lected, the serial clock idles high. when the spi interface is selected, the serial clock idles low. irq# 14 10 17 12 od interrupt output (open-drain, active low). rts# 15 11 18 13 o uart request-to-send. this output can be used for auto rts hardware flow control, auto rs-485 half-duplex direction control or as a general pur - pose output. gpio5 dtr# 16 - 19 - i/o general purpose i/o pin or dtr# output. gpio4 dsr# 17 - 20 - i/o general purpose i/o pin or dsr# input.
xr20m1170 4 i2c/spi uart with 64-byte fifo rev. 1.1.0 pin type: i=input, o=output, i/o= input/output, od=output open drain. reset# 18 12 21 14 i reset (active low) - a longer than 40 ns low pulse on this pin will reset the internal registers and all outputs. the uart transmitter output will be idle and the receiver input will be ignored. cts# 19 13 22 15 i uart clear-to-send. this input can be used for auto cts hardware flow control or as a general purpose input. gpio6 cd# 20 - 23 - i/o general purpose i/o pin or cd# input. gpio7 ri# 21 - 24 - i/o general purpose i/o pin or ri# input. vcc 22 14 1 16 pwr 1.62v to 3.6v power supply. a0 cs# 23 15 2 1 i i 2 c-bus device address select a0 or spi chip select. if i 2 c-bus configuration is selected, this pin along with the a1 pin allows user to change the device?s base address. if spi configuration is selected, this pin is th e spi chip select pin (schmitt-trigger, active low). a1 si 24 16 3 2 i i 2 c-bus device address select a1 or spi data input pin. if i 2 c-bus onfiguration is selected, this pin along with a0 pin allows user to change the device?s base address. if spi configuration is selected, this pin is the spi data input pin. so 1 1 4 3 o spi data output pin. if spi configuration is selected then this pin is a three-stateable output pin. if i2c-bus configuratio n is selected, this pin is undefined and must be left unconnected. - pad pad - - pwr the center pad on the backside of the qfn pack - ages is metallic and is not electrically connected to anything inside the device. it must be soldered on to the pcb and may be optionally connected to gnd on the pcb. the thermal pad size on the pcb should be the approximate size of this center pad and should be solder mask defined. the sol - der mask opening should be at least 0.0025" inwards from the edge of the pcb thermal pad. nc - - - - - no connection. pin description n ame 24-qfn p in # 16-qfn p in # 24-tssop p in # 16-tssop p in # t ype d escription
xr20m1170 5 rev. 1.1.0 i2c/spi uart with 64-byte fifo 1.0 product description the xr20m1170 (m1170) integrates a selectable i 2 c/spi bus interface with an enhanced universal asynchronous receiver and transmitter (uart). the conf iguration registers set is 16550 uart compatible for control, status and data transfer. additionally, th e m1170 has 64-bytes of transmit and receive fifos, automatic rts/cts hardware flow control, automatic x on/xoff and special character software flow control, programmable transmit and receive fifo trigger levels, infrared encoder and decoder (irda 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 16 mbps with 4x sampling clock rate. the xr20m1170 is a 1.62 v to 3.63v device. the m1 170 is fabricated with an advanced cmos process. enhanced features the m1170 uart provides a solution that supports 64 bytes of transmit and receiv e fifo memory, instead of 16 bytes in the industry standard 16c550. the m1170 is designed to work with low supply voltage and high performance data communication systems, that require fast data processing time. increased performance is realized in the m1170 by the larger transmit and receiv e fifos, fifo trigger level control and automatic flow control mechanism. this allows the external processor to ha ndle more networking ta sks within a given time. for example, the 16c550 with a 16 byte fifo, unloads 16 bytes of receive data in 1.53 ms (this example uses a character length of 11 bits, includin g start/stop bits at 115.2 kbps). th is means the external cpu will have to service the receive fifo at 1.53 ms in tervals. however with the 64 byte fi fo in the m1170, the data buffer will not require unloading/loading for 6.1 ms. this increases the service interval giving the external cpu additional time for other applications and re ducing the overall uart interrupt servicing time. in addition, the programmable fifo level trigger interrupt and automatic hardware/software flow cont rol is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. the combination of the above greatly reduces the cpu?s bandwidth requirement, increases performance, and reduces power consumption. the m1170 supports a half-duplex output direction cont rol signaling pin, rts#, to enable and disable the external rs-485 transceiver operation. it automatically s witches the logic state of th e output pin to the receive state after the last stop-bit of the last character has been shifted out of the transmitter. after receiving, the logic state of the output pin switches back to the transmit st ate when a data byte is loaded in the transmitter. the auto rs-485 direction control pin is no t activated after reset. to activate the direction control function, user has to set efcr bit-4 to ?1?. this pin is high for receive state and low for transmit state. the polarity of the rts# pin can be inverted via efcr bit-5. data rate the m1170 is capable of operation up to 16 mbps at 3.3v with 4x internal sampling clock rate, 8 mbps at 3.3v with 8x sampling clock rate, and 4 mbps at 3.3v with 16x internal sampling clock rate. the device can operate with an external 24 mhz crystal on pins xtal1 and xtal2, or external clock source of up to 64 mhz on xtal1 pin. with a typical crystal of 14.7456 mhz and through a software option, the user can set the prescaler bit for data rates of up to 3.68 mbps. the rich feature set of the m1170 is available through th e internal registers. automatic hardware/software flow control, programmable transmit and receive fifo trigge r levels, programmable tx and rx baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. following a power on reset or an external reset, the m1170 is software compatible with previous generation of uarts, 16c450, 16c550 and 16c2550.
xr20m1170 6 i2c/spi uart with 64-byte fifo rev. 1.1.0 2.0 functional descriptions 2.1 cpu interface the m1170 can operate with either an i 2 c-bus interface or an spi interface. the cpu interface is selected via the i2c/spi# input pin. 2.1.1 i 2 c-bus interface the i 2 c-bus interface is co mpliant with the standard-mode and fast-mode i 2 c-bus specifications. the i 2 c- bus interface consists of two lines: serial data (sda) and serial clock (scl). in the standard-mode, the serial clock and serial data can go up to 100 kbps and in the fast-mode, the serial clock and serial data can go up to 400 kbps. the first byte sent by an i 2 c-bus master contains a start bit (sda transition from high to low when scl is high), 7-bit slave address and whether it is a read or write transaction. the next byte is the sub- address that contains the address of the register to access. the m1170 responds to each write with an acknowledge (sda driven low by m1170 for one clock cycl e when scl is high). if the tx fifo is full, the m1170 will respond with a negat ive acknowledge (sda driven high by m1170 for one clock cycle when scl is high) when the cpu tries to write to the tx fifo. the last byte sent by an i 2 c-bus master contains a stop bit (sda transition from low to high when scl is high). see figures 3 - 5 below. for comp lete details, see the i 2 c-bus specifications. f igure 3. i c s tart and s top c onditions sda scl s p start condition stop condition f igure 4. m aster w rites t o s lave (m1170) sw a a ap slave address register address ndata white block: host to uart grey block: uart to host f igure 5. m aster r eads f rom s lave (m1170) sw a ar slave address register address white block: host to uart grey block: uart to host a s slave address ndata anap last data 2
f igure 6. i c d ata f ormats swa a ap slave address data data data transferred (n bytes + acknowledge) master write: start condition write acknowledge acknowledge acknowledge stop condition sraanap slave address data data data transferred (n bytes + acknowledge) master read: start condition read acknowledge acknowledge not acknowledge stop condition sr/wa a slave address r/w slave address data data transferred (n bytes + acknowledge) combined formats: start condition read or write acknowledge acknowledge repeated start condition read or write sr adataap data transferred (n bytes + acknowledge) acknowledge acknowledge stop condition direction of transfer may change at this point xr20m1170 7 rev. 1.1.0 i2c/spi uart with 64-byte fifo 2
xr20m1170 8 i2c/spi uart with 64-byte fifo rev. 1.1.0 2.1.1.1 i 2 c-bus addressing there could be many devices on the i 2 c-bus. to distinguish itself from the other devices on the i 2 c-bus, there are eight possible slave addresses that can be select ed for the m1170 using the a1 and a0 address lines. table 1 below shows the different addresses that can be se lected. note that there are two different ways to select each i2c address. t able 1: xr20m1170 i c a ddress m ap c a ddress vcc vcc 0x60 (0110 000x) vcc gnd 0x62 (0110 001x) vcc scl 0x64 (0110 010x) vcc sda 0x66 (0110 011x) gnd vcc 0x68 (0110 100x) gnd gnd 0x6a (0110 101x) gnd scl 0x6c (0110 110x) gnd sda 0x6e (0110 111x) scl vcc 0x60 (0110 000x) scl gnd 0x62 (0110 001x) scl scl 0x64 (0110 010x) scl sda 0x66 (0110 011x) sda vcc 0x68 (0110 100x) sda gnd 0x6a (0110 101x) sda scl 0x6c (0110 110x) sda sda 0x6e (0110 111x) an i 2 c sub-address is sent by the i 2 c master following the slave address. the sub-address contains the uart register address being accessed. a read or wr ite transaction is determin ed by bit-0 of the slave address. if bit-0 is?0?, then it is a write transaction. if bit- 0 is ?1?, then it is a read tr ansaction. if bit-0 is a logic 1, then it is a read transaction. table 2 below lists the functions of the bits in the i 2 c sub-address. t able 2: i c s ub -a ddress (r egister a ddress ) b it f unction 7 reserved 6:3 uart internal register address a3:a0 2:1 uart channel select ?00? = uart channel a, other values are reserved 0 reserved after the last read or write transaction, the i 2 c-bus master will set the scl signal back to its idle state (high). 2 a1 a0 i 2 2
xr20m1170 9 rev. 1.1.0 i2c/spi uart with 64-byte fifo 2.1.2 spi bus interface the spi interface consists of four lines: serial clock (scl ), chip select (cs#), slave output (so) and slave input (si). the serial clock, slave output and slave input can be as fast as 18 mhz at 3.3v. to access the device in the spi mode, the cs# signal for the m1170 is asserted by the spi master, then the spi master starts toggling the scl signal with the appropriate transaction informat ion. the first bit sent by the spi master includes whether it is a read or write transaction and the uart register being accessed. see table 3 below. t able 3: spi f irst b yte f ormat b it f unction 7 read/write# logic 1 = read logic 0 = write 6:3 uart internal register address a3:a0 2:1 uart channel select ?00? = uart channel a, other values are reserved 0 reserved f igure 7. spi w rite r/w a3 a2 a1 a0 0 0 x d7 d6 d5 d4 d3 d2 d1 d0 sclk si f igure 8. spi r ead r/wa3a2a1a0 0 0 x d7 d6 d5 d4 d3 d2 d1 d0 sclk si so the 64 byte tx fifo can be loaded with data or 64 byte rx fifo data can be unloaded in one spi write or read sequence. f igure 9. spi fifo w rite r/w a3 a2 a1 a0 0 0 x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sclk so last bit
f igure 10. spi fifo r ead sclk d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 last bit r/w a3 a2 a1 a0 0 0x xr20m1170 10 i2c/spi uart with 64-byte fifo rev. 1.1.0 after the last read or writ e transaction, the spi master will set the scl signal back to its idle state (low). 2.2 device reset the reset# input resets the internal r egisters and the serial interfac e outputs in the uart to its default state (see table 16 ). an active low pulse of longer than 40 ns duration will be required to activate the reset function in the device. 2.3 internal registers the m1170 has a set of enhanced registers for contro l, monitoring and data loading and unloading. the configuration register set is compatib le to the industry standard st16c550. these registers function as data holding registers (thr/rhr), interrupt status and control registers (isr/ier), a fifo control register (fcr), receive line status and control registers (lsr/lcr) , modem status and control registers (msr/mcr), programmable data rate (clock) divisor registers (dll/dlm/dld), and a user accessible scratchpad register (spr). beyond the general 16c550 features and capa bilities, the m1170 of fers enhanced feature registers (efr, xon/ xoff 1, xon/xoff 2, tcr, tlr, txlvl, rxlvl, iodir , iostate, iointena, iocontrol, efcr and dld) that provide automatic rts and cts hardware flow control, xo n/xoff software flow control, automatic rs-485 half- duplex direction output enable/disable, tx and rx fi fo level counters, and programmable fifo trigger level control. for complete details, see ?section 3.0, uart inte rnal registers? on page 23 . 2.4 irq# output the irq# interrupt output changes according to the operating mode and enhanced features setup. table 4 and 5 summarize the operating behavior for the transmitter and receiver. also see figures 21 through 35 . t able 4: irq# p in o peration for t ransmitter auto rs485 mode fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) irq# pin no high = a byte in thr low = thr empty high = fifo above trigger level low = fifo below trigger level or fifo empty irq# pin yes high = a byte in thr low = transmitter empty high = fifo above trigger level low = fifo below trigger level or transmitter empty t able 5: irq# p in o peration f or r eceiver fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) irq# pin high = no data low = 1 byte high = fifo below trigger level low = fifo above trigger level
xr20m1170 11 rev. 1.1.0 i2c/spi uart with 64-byte fifo 2.5 crystal oscillator or external clock input the m1170 includes an on-chip oscillato r (xtal1 and xtal2) to produce a cl ock for both uart sections in the device. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. please note that the input xtal 1 is not 5v tolerant and so the maximum at the pin should be vcc. for programming details, see ? ?section 2.6, programmable baud rate ge nerator with fractional divisor? on page 11 .? f igure 11. t ypical oscillator connections c1 22-47 pf c2 22-47 pf y1 1.8432 mhz to 24 mhz r1 0-120 ? (optional) r2 500 ? ? 1 ? xtal1 xtal2 the on-chip oscillator is designed to use an industry stand ard microprocessor cryst al (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 11 ). the programmable baud rate generator is capable of operating with a cr ystal oscillator frequency of up to 24 mhz. however, with an external clock input on xtal1 pin, it can extend it s operation up to 64 mhz (16 mbps serial data rate) at 3.3v with an 4x sampling rate. for further reading on the oscillator circ uit please see the application note dan108 on the exar web site at http://www.exar.com. 2.6 programmable baud rate generator with fractional divisor each uart has its own baud rate generator (brg) with a prescaler for the transmitter and receiver. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the outpu t of the prescaler clocks to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16x, 8x or 4x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (d ll, dlm and dld registers) defaults to the value of ?1? (dll = 0x01, dlm = 0x00 and dld = 0x00 ) upon power-up. therefore, the brg must be programmed during initialization to the operating data rate. the dll and dlm registers provide the integer part of the divisor and the dld register provides the fractional part of the dvisior. the four lower bits of the dld are used to select a value from 0 (for setting 0000) to 0. 9375 or 15/16 (for setting 1111). programming the baud rate generator regist ers dll, dlm and dld provides the capabilit y for selecting the operating data rate. table 6 shows the standard data rates available with a 24mhz crystal or external clock at 16x clock rate. if the pre-scaler is used (mcr bit-7 = 1), the output data ra te will be 4 times less than that shown in table 6 . at 8x sampling rate, these data rates would double and at 4x sampling rate, these data rates would quadruple. also, when using 8x sampling mode, the bit time will have a jitter of 1/16 whenever the dld is non-zero and is an
xr20m1170 12 i2c/spi uart with 64-byte fifo rev. 1.1.0 odd number. when using 4x sampling mode, the bit time will have a jitter of 1/8 whenever dld is non-zero, odd and not a multiple of 4. when using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s): required divisor (decimal)=(xtal1 clock frequency / pre scaler) /(serial data rate x 16), with 16x mode, dld[5:4]=?00? required divisor (decimal)= (xtal1 clock frequency / prescaler / (serial data rate x 8), with 8x mode, dld[5:4] = ?01? required divisor (decimal)= (xtal1 clock frequency / prescaler / (serial data rate x 4), with 4x mode, dld[5:4] = ?10? round( (required divisor - trunc(required divisor ) )*16)/16 + trunc( required divisor), where dlm = trunc(required divisor) >> 8 dll = trunc(required divisor) & 0xff dld = round( (required divisor -trunc(required divisor) )*16) the closest divisor that is obtainable in the m1 170 can be calculated using the following formula: in the formulas above, please note that: trunc (n) = integer part of n. for example, trunc (5.6) = 5. round (n) = n rounded towards the cl osest integer. for example, roun d (7.3) = 7 and round (9.9) = 10. a >> b indicates right shifting the value ?a? by ?b? number of bits. for example, 0x78a3 >> 8 = 0x0078. f igure 12. b aud r ate g enerator xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll, dlm and dld registers prescaler divide by 1 prescaler divide by 4 16x or 8x or 4x sampling rate clock to transmitter and receiver fractional baud rate generator logic
t able 6: t ypical data rates with a 24 mh z crystal or external clock at 16x s ampling required output data rate d ivisor for 16x clock (decimal) d ivisor o btainable in m1170 dlm p rogram v alue (hex) dll p rogram v alue (hex) dld p rogram v alue (hex) d ata e rror r ate (%) 400 3750 3750 e a6 0 0 2400 625 625 2 71 0 0 4800 312.5 312 8/16 1 38 8 0 9600 156.25 156 4/16 0 9c 4 0 10000 150 150 0 96 0 0 19200 78.125 78 2/16 0 4e 2 0 25000 60 60 0 3c 0 0 28800 52.0833 52 1/16 0 34 1 0.04 38400 39.0625 39 1/16 0 27 1 0 50000 30 30 0 1e 0 0 57600 26.0417 26 1/16 0 1a 1 0.08 75000 20 20 0 14 0 0 100000 15 15 0 f 0 0 115200 13.0208 13 0 d 0 0.16 153600 9.7656 9 12/16 0 9 c 0.16 200000 7.5 7 8/16 0 7 8 0 225000 6.6667 6 11/16 0 6 b 0.31 230400 6.5104 6 8/16 0 6 8 0.16 250000 6 6 0 6 0 0 300000 5 5 0 5 0 0 400000 3.75 3 12/16 0 3 c 0 460800 3.2552 3 4/16 0 3 4 0.16 500000 3 3 0 3 0 0 750000 2 2 0 2 0 0 921600 1.6276 1 10/16 0 1 a 0.16 1000000 1.5 1 8/16 0 1 8 0 xr20m1170 13 rev. 1.1.0 i2c/spi uart with 64-byte fifo 2.7 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 64 bytes of fifo which includes a byte-wide transmit holding register (thr) . tsr shifts out every data bit with the 16x/8x/4x internal clock. a bit time is 16 (8 if 8x or 4 if 4x) clock periods (see dld[5:4]). the transmitter sends the start- bit followed by the number of data bits, inserts the prop er parity-bit if enabled, and adds the stop-bit(s). the status of the fifo and tsr are reported in the line status register (lsr[6:5]).
xr20m1170 14 i2c/spi uart with 64-byte fifo rev. 1.1.0 2.7.1 transmit holding regi ster (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 64 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.7.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a tr ansmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. f igure 13. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x or 4x clock ( dld[5:4] ) 2.7.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 64 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed tr igger level. the transmit em pty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. f igure 14. t ransmitter o peration in fifo and f low c ontrol m ode transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo 16x or 8x or 4x clock ( dld[5:4] ) auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg.) txfifo1
xr20m1170 15 rev. 1.1.0 i2c/spi uart with 64-byte fifo 2.8 receiver the receiver section contains an 8-bit receive shift register (rsr) and 64 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x/8x/4x clock (dld [5:4]) for timing. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x/8x/4x clock rate. after 8 clocks (or 4 if 8x or 2 if 4x) the start bit pe riod should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if th ere were any error(s), they are reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the rece ive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay unti l it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data read y time-out interrupt when data is not received for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.8.1 receive holding regi ster (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 64 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains th e first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 15. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x or 8x or 4x clock ( dld[5:4] ) receive data characters data bit validation error tags in lsr bits 4:2
f igure 16. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x or 8x or 4x clock ( dld[5:4] ) error tags (64-sets) error tags in lsr bits 4:2 receive data characters fifo trigger=16 example : - rx fifo trigger level selected at 16 bytes (see note below) data fills to halt level data falls to resume level data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills to the halt level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls to the resume level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1. 64 bytes by 11-bit wide fifo xr20m1170 16 i2c/spi uart with 64-byte fifo rev. 1.1.0 2.9 auto rts (hardware) flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 17 ): ? enable auto rts flow control using efr bit-6. ? the auto rts function must be started by asserting rts# output pin (mcr bit-1 to logic 1 after it is enabled). if using the auto rts interrupt: ? enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin makes a transition from low to high: isr bit-5 will be set to logic 1. 2.10 auto rts halt and resume the rts# pin will not be forced high (rts off) until the receive fifo r eaches the halt leve l (tcr[3:0]). the rts# pin will return low after the rx fifo is unl oaded to the resume leve l (tcr[7:4]). under these conditions, the m1170 will continue to ac cept data if the remote uart contin ues to transmit data. it is the responsibility of the user to ensure t hat the halt level is greater than th e resume level. if interrupts are used, it is recommended that halt level > rx trigger level > resume level. t he auto rts function is initiated when the rts# output pin is asserted low (rts on). 2.11 auto cts flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 17 ): ? enable auto cts flow control using efr bit-7. if using the auto cts interrupt: ? enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (high): is r bit-5 will be set to 1, and uart will suspend transmission as soon as
xr20m1170 17 rev. 1.1.0 i2c/spi uart with 64-byte fifo the stop bit of the character in process is shifted ou t. transmission is resumed after the cts# input is re- asserted (low), indicating more data may be sent. f igure 17. a uto rts and cts f low c ontrol o peration rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1 the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow.
xr20m1170 18 i2c/spi uart with 64-byte fifo rev. 1.1.0 2.12 auto xon/xoff (software) flow control when software flow control is enabled ( see table 15 ), the m1170 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 character value(s). if receive character(s) (rx) match the programmed values, the m1170 will halt transmission (tx) as soon as th e current character has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspen sion due to a match of the xoff character, the m1170 will monitor the receive data stream for a match to th e xon-1,2 character. if a match is found, the m1170 will resume operation and clear the flags (isr bit-4). upon power-up, the contents of the xon/xoff 8-bit flow control registers to 0x00. the user can write any xon/ xoff value desired for software flow control. these registers are not reset by a hardware or software reset. different conditions can be set to detect xon/xoff characters ( see table 15 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the m1170 compares two consecutive receive characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmissions accordingly. under the above described fl ow control mechanisms, flow control characters are not placed (stacked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the m1 170 automatically sends the xoff-1,2 via the serial tx output to the re mote modem when the rx fifo reaches the halt level (tcr[3:0]). to clear this condition, the m1170 will trans mit the programmed xon-1,2 ch aracters as soon as rx fifo falls down to the resume level. 2.13 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the m1170 compares each incoming receive character wit h xoff-2 data. if a match exists, the received data will be transferred to fifo and isr bit- 4 will be set to indicate detection of special character. although the internal register table shows xon, xoff registers with ei ght bits of character information, the actual number of bits is dependent on the programmed word length. line cont rol register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. 2.14 auto rs485 half-duplex control the auto rs485 half-duplex direction control changes th e behavior of the transmitter when enabled by efcr bit-4. it also changes the behavior of the transmit empty interrupt (see table 4 ). when idle, the auto rs485 half-duplex direction control signal (rts#) is high fo r receive mode. when data is loaded into the thr for transmission, the rts# output is automatically asserted lo w prior to sending the data. after the last stop bit of the last character that has been transmitted, the rts# si gnal is automatically de-asserted. this helps in turning around the transceiver to re ceive the remote station?s response. when the host is ready to transmit next polling data packet, it only has to load data bytes to the tran smit fifo. the transmitter au tomatically re-asserts rts# (low) output prior to sending the data. the polarity of the rts# output pin can be inverted by setting efcr[5] = 1. 2.14.1 normal multidrop mode normal multidrop mode is enabled when efcr bit-0 = 1 and efr bit-5 = 0 (special character detect disabled). the receiver is set to force parity 0 (lcr[5:3] = ?111?) in orde r to detect address bytes. with the receiver initially di sabled, it ignores all the data bytes (parity bit = 0) until an address byte is received (parity bit = 1). this address byte will cause the uart to set the parity error. the uart will generate an lsr interrupt and place the address byte in the rx fifo. the software then examines the byte and enables the receiver if the address matches its slave addres s, otherwise, it does not enable the receiver. if the receiver has been enabled, the receiver will receiv e the subsequent data. if an address byte is received, it will generate an lsr inte rrupt. the software again examines the byte and if the addr ess matches its slave
xr20m1170 19 rev. 1.1.0 i2c/spi uart with 64-byte fifo address, it does not have to anything. if the address does not match its slave address, then the receiver should be disabled. 2.14.2 auto address detection auto address detection mode is enabled when efcr bit-0 = 1 and efr bit-5 = 1. the desired slave address will need to be written into the xoff2 register. the receiver will try to detect an address by te that matches the porgrammed character in the xoff2 register. if the received byte is a data byte or an address byte that does not match the programmed character in the xoff2 register, the receiver will discard these data. upon receiving an address byte that matc hes the xoff2 character, the receiver will be automatically enabled if not already enabled, and the address character is pushed into the rx fifo along with the parity bit (in place of the parity error bit). the receiver also generates an lsr interrupt. the re ceiver will then receive the subsequent data. if another address byte is received and this address does not match the programmed xoff2 character, then the receiver will automatically be disabled and the address byte is ig nored. if th e address byte matches xoff2, the receiver will put this byte in the rx fifo along with the pa rity bit in the parity error bit.
xr20m1170 20 i2c/spi uart with 64-byte fifo rev. 1.1.0 2.15 infrared mode the m1170 uart includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0 and 1.1. the irda 1.0 standa rd that stipulates the infrared encoder sends out a 3/16 of a bit wide high-pulse for each ?0? bit in the transmit data stream with a data rate up to 115.2 kbps. for the irda 1.1 standard, the infrared encoder sends out a 1/4 of a bit time wide high-pulse for each "0" bit in the transmit data stream with a data rate up to 1.152 mb ps. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 18 below. the infrared encoder and decoder are enabled by setting mc r register bit-6 to a ?1?. with this bit enabled, the infrared encoder and decoder is compatible to the irda 1.0 standard. for the infrared encoder and decoder to be compatible to the irda 1. 1 standard, efcr bit-7 will also need to be set to a ?1?. when the infr ared feature is enabled, the transmit data output, tx, idles lo w. likewise, the rx input also idles low, see figure 18 . the wireless infrared decoder receives the input pulse fr om the infrared sensing diode on the rx pin. each time it senses a light pulse, it retu rns a logic 1 to the data bit stream. after power-up, the infrared mode can be controlled via mcr bit-6. f igure 18. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 or 1/4 bit time irencoder-1 character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse (rx pin)
xr20m1170 21 rev. 1.1.0 i2c/spi uart with 64-byte fifo 2.16 sleep mode with auto wake-up the m1170 supports low voltage system designs, henc e, a sleep mode is included to reduce its power consumption when the chip is not actively used. all of these conditions must be sati sfied for the m1170 to enter sleep mode: no interrupts pending for the m1170 (isr bit-0 = 1) sleep mode of both channels are enabled (ier bit-4 = 1) modem inputs are not toggling (msr bits 0-3 = 0) rx input pin is idling high the m1170 stops its crystal oscillator to conserve power in the sleep mode. user can check the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the m1170 resumes normal operation by any of the following: a receive data start bit transition (high to low) a data byte is loaded to the transmitter, thr or fifo a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the m1170 is awakened by any one of the above condit ions, it will return to th e sleep mode automatically after all interrupting conditions have been servic ed and cleared. if the m1170 is awakened by the modem inputs, a read to the msr is requ ired to reset the modem inputs. in any case, the sleep mode will not be entered while an interrupt is pending. the m1170 will stay in the sleep mode of operation until it is disabled by setting ier bit-4 to a logic 0. if the serial clock, serial data, and modem input lines remain steady when the m1170 is in sleep mode, the maximum current will be in the micr oamp range as specified in the dc electrical characteristics on page 41 . a word of caution: owing to the star ting up delay of the crystal oscillato r after waking up from sleep mode, the first few receive characters may be lost. the number of ch aracters lost during the restart also depends on your operating data rate. more characters are lost when operati ng at higher data rate. also, it is important to keep rx input idling high or ?marking? condition during slee p mode to avoid receiving a ?break? condition upon the restart. this may occur when the external interface tr ansceivers (rs-232, rs-485 or another type) are also put to sleep mode and cannot maintain the ?marking? condit ion. to avoid this, the designer can use a 47k-100k ohm pull-up resistor on the rx input pin.
xr20m1170 22 i2c/spi uart with 64-byte fifo rev. 1.1.0 2.17 internal loopback the m1170 uart provides an internal loopback capability for syst em diagnostic pur poses. the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally. figure 19 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx, rts# and dtr# pins are held while the cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input pin must be held high during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. also , auto rts/cts flow control is not supported during internal loopback. f igure 19. i nternal l oop b ack tx rx modem / general purpose control logic internal data bus lines and control signals rts# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) cts# dtr# dsr# ri# cd# op1# rts# cts# dtr# dsr# ri# cd# vcc op2#
xr20m1170 23 rev. 1.1.0 i2c/spi uart with 64-byte fifo 3.0 uart internal registers the complete register set is shown below in table 7 and table 8 . t able 7: uart internal register addresses a ddress r egister r ead /w rite c omments 16c550 c ompatible r egisters 0x00 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0x00 dll - divisor lsb read/write lcr[7] = 1, lcr 0xbf 0x01 dlm - divisor msb read/write 0x02 dld - divisor fractional read/write lcr[7] = 1, lcr 0xbf, efr[4] = 1 0x01 ier - interrupt enable register read/write lcr[7] = 0 0x02 isr - interrupt status register fcr - fifo control register read-only write-only 0x03 lcr - line control register read/write 0x04 mcr - modem control register read/write lcr 0xbf 0x05 lsr - line status register read-only 0x06 msr - modem status register read-only see table 12 0x07 spr - scratch pad register read/write see table 13 0x06 tcr - transmission control register read/write see table 12 0x07 tlr - trigger level register read/write see table 13 0x08 txlvl - transmit fifo level read-only lcr[7] = 0 0x09 rxlvl - receive fifo level read-only 0x0a iodir - gpio direction control register read/write 0x0b iostate - gpio state register read/write 0x0c iointena - gpio interrupt enable register read/write 0x0d reserved - 0x0e iocontrol - gpio control register read/write 0x0f efcr - extra features control register read/write 0x02 efr - enhanced function register read/write lcr = 0xbf 0x04 xon-1 - xon character 1 read/write 0x05 xon-2 - xon character 2 read/write 0x06 xoff-1 - xoff character 1 read/write 0x07 xoff-2 - xoff character 2 read/write
xr20m1170 24 i2c/spi uart with 64-byte fifo rev. 1.1.0 . t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddr r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0x00 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0x00 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x01 ier rd/wr 0/ 0/ 0/ 0/ modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable cts int. enable rts int. enable xoff int. enable sleep mode enable 0x02 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 int source bit-5 int source bit-4 0x02 fcr wr r x f i f o trigger rx fifo trigger 0/ 0/ 0 tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0x03 lcr rd/wr divisor enable set tx break set par - ity even parity parity enable stop bits word length bit-1 word length bit-0 0x04 mcr rd/wr 0/ 0/ 0/ internal lopback enable op2# (internal) op1# (internal)/ rts# output control dtr# output control lcr z 0xbf clock pres - caler select ir mode xonany enable tcr and tlr 0x05 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx framing error rx par - ity error rx overrun error rx data ready 0x06 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# see table 12 0x07 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 see table 13 0x06 tcr rd/wr resume bit-3 resume bit-2 resume bit-1 resume bit-0 halt bit-3 halt bit-2 halt bit-1 halt bit-0 see table 12 0x07 tlr rd/wr rx trig bit-3 rx trig bit-2 rx trig bit-1 rx trig bit-0 tx trig bit-3 tx trig bit-2 tx trig bit-1 tx trig bit-0 see table 13 0x08 txlvl rd/wr 0 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x09 rxlvl rd/wr 0 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x0a iodir rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr20m1170 25 rev. 1.1.0 i2c/spi uart with 64-byte fifo 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 15. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 13. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive interr upts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: 0x0b iostate rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x0c iointena rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x0d reserved - 0 0 0 0 0 0 0 0 0x0e iocontrol rd/wr 0 0 0 0 uart sw reset 0 gpio or modem io iolatch 0x0f efcr rd/wr fast ir mode 0 auto rs485 invert auto rs485 enable 0 tx disable rx disable 9-bit mode baud rate generator divisor 0x00 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr z 0xbf 0x01 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x02 dld rd/wr bit-7 bit-6 4x mode 8x mode frac - tional divisor bit-3 frac - tional divisor bit-2 frac - tional divisor bit-1 frac - tional divisor bit-0 lcr[7]=1 lcr z 0xbf efr[4]=1 enhanced registers 0x02 efr rd/wr auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5], dld soft- ware flow cntl bit-3 software flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 lcr=0 x bf 0x04 xon1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x05 xon2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x06 xoff1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x07 xoff2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 8: internal registers description. s haded bits are enabled when efr b it -4=1 a ddr r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr20m1170 26 i2c/spi uart with 64-byte fifo rev. 1.1.0 a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the xr20m1170 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character in th e non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. x logic 0 = disable the receive data ready interrupt (default). x logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when spaces in the fifo is above the pr ogrammed trigger level in the fifo mode. if the thr is empty when this bit is enabled , an interrupt will be generated. x logic 0 = disable transmit ready interrupt (default). x logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3, 4 or 7 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fi fo. lsr bit-1 generates an interrupt immediately when the character has been received. lsr bit-7 is set if any character in the rx fifo has a parity or framing error, or is a break character. lsr[4:2] always show the error stat us for the received character available for reading from the rx fifo. if ier[2] = 1, an ls r interrupt will be generated as long as ls r[7] = 1, ie. the rx fifo contains at lease one character with an error. x logic 0 = disable the receiver line status interrupt (default). x logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable x logic 0 = disable the modem status register interrupt (default). x logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr bit-4 = 1) x logic 0 = disable sleep mode (default). x logic 1 = enable sleep mode. see sleep mode section for further details.
xr20m1170 27 rev. 1.1.0 i2c/spi uart with 64-byte fifo ier[5]: xoff interrupt enable (requires efr bit-4=1) x logic 0 = disable the software flow cont rol, receive xoff interrupt (default). x logic 1 = enable the receive xoff interrupt. see software flow control section for details. ier[6]: rts# output interrupt enable (requires efr bit-4=1) x logic 0 = disable the rts# interrupt (default). x logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high. ier[7]: cts# input interrupt enable (requires efr bit-4=1) x logic 0 = disable the cts# interrupt (default). x logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt level to be se rviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 9 , shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: x lsr is by any of the lsr bits 1, 2, 3, 4 and 7. x rxrdy is by rx trigger level. x rxrdy time-out is by a 4-char plus 12 bits delay timer. x txrdy is by tx trigger level or tx fifo empty (or transmitter empty in auto rs-485 control). x msr is by any of the msr bits 0, 1, 2 and 3. x gpio is when any of the gpio inputs toggle. x receive xoff/special character is by det ection of a xoff or special character. x cts# is when its transmitter toggles the input pin (f rom low to high) during auto cts flow control. x rts# is when its receiver toggles the output pin (f rom low to high) during auto rts flow control. 4.4.2 interrupt clearing: x lsr interrupt is cleared by reading all characters with errors out of the rx fifo. x rxrdy interrupt is cleared by reading data until fifo fa lls below the trigger level. x rxrdy time-out interrupt is cleared by reading rhr. x txrdy interrupt is cleared by a read to the isr register or writing to thr. x msr interrupt is cleared by a read to the msr register. x gpio interrupt is cleared by reading the iostate register. x xoff interrupt is cleared when xon character(s) is received. x special character interrupt is cleared by a read to isr. x rts# and cts# flow control interrupts are cleared by a read to the msr register.
xr20m1170 28 i2c/spi uart with 64-byte fifo rev. 1.1.0 ] t able 9: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 1 1 0 0 0 0 gpio (general purpose inputs) 7 0 1 0 0 0 0 rxrdy (received xoff or special character) 8 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default) isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority leve ls (see interrupt source table 9 ). isr[4]: xoff/xon or special character interrupt status this bit is set when efr[4] = 1 and ier[5] = 1. isr bit-4 indicates that the receiver detected a data match of the xoff character(s). if this is an xoff interrupt, it is cleared when xon is received. if it is a special character interrupt, it is cleared by reading isr. isr[5]: rts#/cts# interrupt status this bit is enabled when efr[4] = 1. isr bit-5 indicates that the cts# or rts# has been de-asserted. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fi fos and set the transmit/receive fifo trigger levels. the fifo mode is defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed.
xr20m1170 29 rev. 1.1.0 i2c/spi uart with 64-byte fifo fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1 ? and requires at least 3 xtal clocks to reset. ? logic 0 = no receive fifo reset (default) ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1 ? and requires at least 3 xtal clocks to reset. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: reserved this is a legacy register bit that does not have any functionality in the xr20m1170. fcr[5:4]: transmit fifo trigger select (requires efr bit-4=1) (logic 0 = default, tx trigger level = 1) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of spaces in the fifo is above the selected trigge r level, or when it gets em pty in case that the fifo did not get filled over the trig ger level on last re-load. table 10 shows the selections. the uart will issue a transmit interrupt when the number of available spaces in the fifo is less than the transmit tr igger level. table 10 shows the selections. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) these 2 bits are used to se t the trigger level for the receive fifo. th e uart will issue a rece ive interrupt when the number of the characters in t he fifo is greater than the receive trigger level or when a receive data timeout occurs (see ?section 2.8, receiver? on page 15 ). t able 10: t ransmit and r eceive fifo t rigger l evel s election b it -7 b it -6 b it -5 bit -4 r eceive t rigger l evel ( characters ) t ransmit t rigger l evel ( spaces ) 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 fcr fcr fcr fcr
xr20m1170 30 i2c/spi uart with 64-byte fifo rev. 1.1.0 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. w ord length 0 0 5 0 1 6 (default) 1 0 7 1 1 8 lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2 (default) lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 11 for parity select ion summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received (default). lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format. ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format (default). bit-1 bit-0 bit-2
xr20m1170 31 rev. 1.1.0 i2c/spi uart with 64-byte fifo lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced (default). ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. t able 11: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0? lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space", low state). this condition remains, unt il disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?space?, low, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll, dlm and dld) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/mod em interface signals or g eneral purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? logic 0 = force dtr# output high (default). ? logic 1 = force dtr# output low. mcr[1]: rts# output the rts# pin is a modem control output and may be used for automatic hardware flow control by enabled by efr bit-6. the rts# pin can also be used for auto rs485 half-duplex direction control enabled by fctr bit- 3. if the modem interface is not used, this out put may be used as a general purpose output. ? logic 0 = force rts# high (default). ? logic 1 = force rts# low.
xr20m1170 32 i2c/spi uart with 64-byte fifo rev. 1.1.0 mcr[2]: op1# / tcr and tlr enable op1# is not available as an output pin on the m1170. but it is available for use during internal loopback mode (mcr[4] = 1). in the internal loopbac k mode, this bit is used to write the state of the modem ri# interface signal. this bit is also used to select between the msr and t cr registers at address offset 0x6 and the spr and tlr registers at address offset 0x7. table 12 and table 13 below shows how these registers are accessed. t able 12: r egister at a ddress o ffset 0 x 6 efr[4] mcr[2] register at address offset 0x6 0 x modem status register (msr) 1 0 modem status register (msr) 1 1 trigger control register (tcr) t able 13: r egister at a ddress o ffset 0 x 7 efr[4] mcr[2] register at address offset 0x7 0 x scratchpad register (spr) 1 0 scratchpad register (spr) 1 1 trigger level register (tlr) mcr[3]: op2# op2# is not available as an output on the m1170 but can be controlled in internal loopback mode. ? logic 0 = op2# set high(default). ? logic 1 = op2# set low. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 19 . mcr[5]: xon-any enable (requires efr bit-4=1 to write to this bit) ? logic 0 = disable xon-any function (default). ? logic 1 = enable xon-any function. in this mode, any rx character re ceived will resume transmit operation. the rx character will be loaded into the rx fifo, unless the rx characte r is an xon or xo ff character and the m1170 is programmed to use the xon/xoff flow control. mcr[6]: ir mode enable (requires efr bit-4=1 to write to this bit) this bit enables the infrared mode and/or controls the infrared mode after power-up. see ?section 2.15, infrared mode? on page 20 for complete details. ? logic 0 = reserved (default). ? logic 1 = enable ir mode.
xr20m1170 33 rev. 1.1.0 i2c/spi uart with 64-byte fifo mcr[7]: clock prescaler select (requires efr bit-4=1 to write to this bit) x logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). x logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. lsr[0]: receive data ready indicator x logic 0 = no data in receive holding register or fifo (default). x logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun error flag x logic 0 = no overrun error (default). x logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error tag x logic 0 = no parity error (default). x logic 1 = parity error. the receive character in rhr does not have correct parity information and is suspect. this error is associated with the char acter available for reading in rhr. lsr[3]: receive data framing error tag x logic 0 = no framing error (default). x logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break error tag x logic 0 = no break condition (default). x logic 1 = the receiver received a break signal (rx wa s low for at least one char acter frame time). in the fifo mode, only one break character is loaded into the fifo. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to th e transmit shift register. t he bit is reset to logic 0 concurrently with the data loading to the transmit holding r egister by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bi t is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty.
xr20m1170 34 i2c/spi uart with 64-byte fifo rev. 1.1.0 lsr[7]: receive fifo data error flag x logic 0 = no fifo error (default). x logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in any of the bytes in the rx fifo. 4.9 modem status register (msr) - read only this register provides the current state of the modem interf ace input signals. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag x logic 0 = no change on cts# input (default). x logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta ds r# input flag x logic 0 = no change on dsr# input (default). x logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag x logic 0 = no change on ri# input (default). x logic 1 = the ri# input has changed from a low to high, ending of the ringing signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag x logic 0 = no change on cd# input (default). x logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if ms r interrupt is enab led (ier bit-3). msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a high on the cts# pin will stop uart transmitte r as soon as the current character has finished transmission, and a low will re sume data transmission. normally ms r bit-4 bit is the complement of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status normally this bit is the complement of the dsr# input. in the loopback mode , this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the complement of the ri# input. in the loopback mode th is bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used.
xr20m1170 35 rev. 1.1.0 i2c/spi uart with 64-byte fifo msr[7]: cd input status normally this bit is the complement of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becom es 0xff (default) after a power off-on cycle. there are also two other registers (tlr and fifo rdy) that share the same address location as the scratch pad register. see table 13 . 4.11 transmission control register (tcr) - read/write (requires efr bit-4 = 1) this register replaces msr and is access ible only when mcr[2] = 1. this 8- bit register is used to store the rx fifo threshold levels to halt/res ume transmission during hardware or software flow control. tcr[3:0]: rx fifo halt level a value of 0-60 (decimal value of tcr[3:0] multiplied by 4) can be selected as the halt level. when the rx fifo is greater than or equal to this value, the rts# output will be de-asserted if auto rts flow control is used or the xoff character(s) will be transmitted if auto xo n/xoff flow control is used . it is recommended that this value is greater than the rx trigger level. tcr[7:4]: rx fifo resume level a value of 0-60 (decimal value of tc r[7:4] multiplied by 4) can be selected as the resume level. when the rx fifo is less than or equal to this value, the rts# output will be re-asser ted if auto rts flow control is used or the xon character(s) will be transmitted if auto xon/xo ff flow control is used. it is recommended that this value is less than th e rx trigger level. 4.12 trigger level register (tlr) - read/write (requires efr bit-4 = 1) this register replaces spr and is a ccessible under the conditions listed in table 13 . this 8-bit register is used to store the rx and tx fifo trigger levels used for interrupts. tlr[3:0]: tx fifo trigger level a value of 4-60 (decimal value of tcr[3:0] multiplied by 4) can be selected as the tx fifo trigger level. when the number of available spaces in the tx fifo is greater than or equal to this value, a transmit ready interrupt is g enerated. for any non-zero value, tcr[3:0] will be us ed as the tx fifo trigger level. if tcr[3:0] = 0x0, then the tx fi fo trigger level is the value selected by fcr[5:4]. see table 10 . tlr[7:4]: rx fifo trigger level a value of 4-60 (decimal value of tcr[7:4] multiplied by 4) can be selected as the rx fifo trigger level. when the number of characters received in the rx fifo is greater than or equal to this value, a receive data ready interrupt is generated (a rece ive data timeout interrupt is independent of the rx fifo trigger level and can be generated any time there is at least 1 byte in the rx fifo and the rx input has been idle for the timeout period described in ?section 2.8, receiver? on page 15 ). for any non-zero value, tcr[7:4] will be used as the rx fifo trigger level. if tcr[7:4] = 0x0, then the rx fifo trigger leve l is the value selected by fcr[7:6]. see table 10 . 4.13 transmit fifo level register (txlvl) - read-only this register reports the number of spaces available in the tx fifo. if the tx fifo is empty, the txlvl register will report that there are 64 spac es available. if the tx fifo is fu ll, the txlvl register will report that there are 0 spaces available. 4.14 receive fifo level regi ster (rxlvl) - read-only this register reports the number of characters availabl e in the rx fifo. if the rx fifo is empty, the rxlvl register will report that there are 0 ch aracters available. if the rx fifo is full, the rxlvl register will report that there are 64 characcters available.
xr20m1170 36 i2c/spi uart with 64-byte fifo rev. 1.1.0 4.15 gpio direction register (iodir) - read/write this register is used to program the direction of t he gpio pins. bit-7 to bit-0 controls gpio7 to gpio0. x logic 0 = set gpio pin as input x logic 1 = set gpio pin as output 4.16 gpio state register (iostate) = read/write this register reports the state of all gpio pins duri ng a read and writes to any gpio that is an output. x logic 0 = set output pin low x logic 1 = set output pin high 4.17 gpio interrupt enable regi ster (iointena) - read/write this register enables the interrupt for the gpio pi ns. the interrupts for gpio[7:4] are only enabled if iocontrol[1] = 0. if iocontrol[0] = 1 (gpio pins are selected as modem ios) , then iointena[7:4] will have no effect on gpio[7:4]. x logic 0 = a change in the inpu t pin will not generate an interrupt x logic 1 = a change in the in put will generate an interrupt 4.18 gpio control register (iocontrol) - read/write iocontrol[7:4]: reserved iocontrol[3]: uart software reset writing a logic 1 to this bit will reset th e device. once the device is reset, this bit will automatically be set to a logic 0. iocontrol[2]: reserved iocontrol[1]: gpio[7:4 ] or modem io select this bit controls whether gpio[7:4] behave as gpio pins or as modem io pins (ri#, cd#, dtr#, dsr#) x logic 0 = gpio[7:4] behave as gpio pins x logic 1 = gpio[7:4] behave as ri#, cd#, dtr#, dsr# iocontrol[0]: io latch this bit enable/disable gpio inputs latching. x logic 0 = gpio input values are not latched. a change in any gpio input generates an interrupt. a read of the iostate register clears the interrupt. if the input goe s back to its initial logic st ate before the input register is read, then the interrupt is cleared. x logic 1 = gpio input values are latched. a change in the gpio input generates an interrupt and the input logic value is loaded in the bit of the corresponding input state register (iostate). a read of the iostate register clears the interrupt. if the input pin goes back to its initial logic state before the interrupt register is read, then the interrupt is not cleared and the corresponding bit of the iostate register keeps the logic value that generated the interrupt. 4.19 extra features control register (efcr) - read/write efcr[7]: irda mode this bit selects between the slow and fast irda modes. see ?section 2.15, infrared mode? on page 20 for complete details. x logic 0 = irda version 1.0, 3/16 pulse ratio, data rate up to 115.2 kbps x logic 1 = irda version 1.1, 1/4 pulse ratio, data rate up to 1.152 mbps
xr20m1170 37 rev. 1.1.0 i2c/spi uart with 64-byte fifo efcr[6]: reserved efcr[5]: auto rs-485 polarity inversion this bit changes th e polarity of the auto rs-485 half-duplex dire ction control output (rts #). this bit will only affect the behavior of the rts# output if efcr[4] = 1. see ?section 2.14, auto rs485 half-duplex control? on page 18 for complete details. x logic 0 = rts# output is low when transmitting and high when receiving. x logic 1 = rts# output is high when transmitting and low when receiving. efcr[4]: auto rs-485 enable this bit enables the rts# output as the auto rs-485 half-duplex direction control output. see ?section 2.14, auto rs485 half-duplex control? on page 18 for complete details. x logic 0 = rts# output can be used for auto rts ha rdware flow control or as a general purpose output. x logic 1 = rts# output enabled as the auto rs-485 half-duplex direction control output. efcr[3]: reserved efcr[2]: transmitter disable uart does not send serial data out on the tx output pin, bu t the tx fifo will continue to receive data from cpu until full. any data in the tsr will be sent out before the trasnmitter goes into disable state. x logic 0 = transmitter is enabled x logic 1 = transmitter is disabled efcr[1] = receiver disable uart will stop receiving data immediately once this bit is set to a logic 1. any data that is being received in the tsr will be received correctly and sent to the rx fifo. x logic 0 = receiver is enabled x logic 1 = receiver is disabled efcr[0]: 9-bit or mu ltidrop mode enable this bit enables 9-bit or multidrop mode. see ?section 2.14, auto rs485 half-duplex control? on page 18 for complete details. x logic 0 = normal 8-bit mode x logic 1 = enable 9-bit or multidrop mode 4.20 baud rate generator registers (dll, dlm and dld[3:0]) - read/write these registers make-up the value of the baud rate divi sor. the concatenation of the contents of dlm and dll is a 16-bit value is then added to dld[3:0]/16 to achieve the fractional baud rate divisor. dld must be enabled via efr bit-4 before it can be accessed. see?programmable baud rate generator with fractional divisor? on page 11. dld[5:4]: sampli ng rate select
xr20m1170 38 i2c/spi uart with 64-byte fifo rev. 1.1.0 these bits select the data sampling rate. by default, the data sampling rate is 16x. the maximum data rate will double if the 8x mode is selected and will quadruple if th e 4x mode is selected. see table 14 below. t able 14: s ampling r ate s elect s ampling r ate 0 0 16x 0 1 8x 1 x 4x dld[7:6]: reserved 4.21 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 15 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. t able 15: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2, receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2, xoff1 and xoff2 dld[5] dld[4]
xr20m1170 39 rev. 1.1.0 i2c/spi uart with 64-byte fifo efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 2 and 5-7, tcr, tlr and dld to be modified. after modifying any enh anced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software fr om altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. x logic 0 = modification disable/latch enhanced features. ie r bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 2 and 5-7, and dld are saved to retain the user settings. af ter a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7, and dld are set to a logic 0 to be compatible with st16c550 mode (default). x logic 1 = enables the above-mentioned register bits to be modified by the user. efr[5]: special character detect enable x logic 0 = special character detect disabled (default). x logic 1 = special character detect enabled. the ua rt compares each incomi ng receive character with data in xoff-2 register. if a match exists, the receive data will be transfer red to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit of the receive character. if flow control is set for comparing xon1, xo ff1 (efr [1:0]= ?10?) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]= ?01?) then flow control works normally, but xoff2 will not go to the fifo, and will ge nerate an xoff interrupt and a special character interrupt, if enabled via ier bit-5. efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is selected, an interrupt will be generated when the receive fifo is fi lled to the programm ed trigger level and rts de-asserts high at the programmed halt level. rts# will return low when fi fo data falls below the programmed resume level. the rts# output must be asserted (low) before the auto rts can take effect. rts# pin will function as a general purpose out put when hardware flow control is disabled. x logic 0 = automatic rts flow control is disabled (default). x logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. x logic 0 = automatic cts flow control is disabled (default). x logic 1 = enable automatic cts flow control. data transmission stops when cts# input de-asserts high. data transmission resumes when cts# returns low. 4.21.1 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, see table 8 .
t able 16: uart reset states dlm, dll dlm = 0x00 and dll = 0x01 [1] dld bits 7-0 = 0x00 rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x1d mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff [1] tcr bits 7-0 = 0x0f tlr bits 7-0 = 0x00 txlvl bits 7-0 = 0x40 rxlvl bits 7-0 = 0x00 iodir bits 7-0 = 0x00 iostate bits 7-0 = 0x00 iointena bits 7-0 = 0x00 iocont bits 7-0 = 0x00 efcr bits 7-0 = 0x00 efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 [1] xon2 bits 7-0 = 0x00 [1] xoff1 bits 7-0 = 0x00 [1] xoff2 bits 7-0 = 0x00 [1] i/o signals tx high rts# high dtr# high irq# high xr20m1170 40 i2c/spi uart with 64-byte fifo rev. 1.1.0 n ote : [1] only resets to these values du ring a power up. they do not reset when the reset# pin is asserted or during software reset iocont[3] = 1. registers reset state reset state
xr20m1170 41 rev. 1.1.0 i2c/spi uart with 64-byte fifo 5.0 electrical characteristics absolute maximum ratings power supply range 4 volts voltage at any pin gnd-0.3v to 4v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package therma l resistance data ( margin of error: 15% ) thermal resistance (24-qfn) theta-ja = 38 o c/w, theta-jc = 26 o c/w thermal resistance (16-qfn) theta-ja = 40 o c/w, theta-jc = 26 o c/w thermal resistance (24-tssop) theta-ja = 84 o c/w, theta-jc = 16 o c/w thermal resistance (16-tssop) theta-ja = 105 o c/w, theta-jc = 20 o c/w dc electrical characteristics ta= -40 o to +85 o c, vcc is 1.62v to 3.63v s ymbol p arameter l imits 10% m in m ax l imits 10% m in m ax l imits 10% m in m ax u nits c onditions v ilck clock input low level -0.3 0.3 -0.3 0.6 -0.3 0.6 v v ihck clock input high level 1.4 vcc 1.8 vcc 2.4 vcc v v il input low voltage -0.3 0.2 -0.3 0.5 -0.3 0.8 v v ih input high voltage 1.4 vcc 1.8 vcc 2.0 vcc v v ol output low voltage 0.4 0.4 0.4 v v i ol = 4 ma i ol = 2 ma i ol = 1.5 ma v oh output high voltage 1.4 1.8 2.0 v v i oh = -1 ma i oh = -400 ua i oh = -200 ua i il input low leakage current 10 10 10 ua i ih input high leakage current 10 10 10 ua c in input pin capacitance 5 5 5 pf i cc power supply current 250 250 500 ua xtal1 = 2 mhz i sleep sleep current 15 20 30 ua see test 1 test 1: the following inputs must rema in steady at vcc or gnd state to minimize sleep current: serial data, serial clock and all modem inputs ar e idle. also, rx input must idle high while asleep. floating inputs will result in sleep currents in the ma range. 1.8v 2.5v 3.3v
ac electrical characteristics - uart clock unless otherwise noted: ta=-40 o to +85 o c, vcc=1.62 - 3.63v s ymbol p arameter l imits 5% m in m ax l imits 10% m in m ax l imits 10% m in m ax l imits 10% m in m ax u nit xtal1 uart crystal oscillator 24 24 24 24 mhz eclk uart external clock 32 24 50 64 mhz t eclk external clock time period 1/ eclk 1/ eclk 1/ eclk 1/ eclk ns f igure 20. c lock t iming external clock vihck vilck t eclk xr20m1170 42 i2c/spi uart with 64-byte fifo rev. 1.1.0 1.8v 1.8v 2.5v 3.3v
ac electrical characte ristics - i2c-bus ti ming specifications unless otherwise noted: ta=-40 o to +85 o c, vcc=1.62 - 3.63v s ymbol p arameter s tandard m ode i2c-b us m in m ax f ast m ode i2c-b us m in m ax u nit f scl operating frequency 0 100 0 400 khz t buf bus free time between stop and start 4.7 1.3 s t hd;sta start condition hold time 4.0 0.6 s t su;sta start condition setup time 4.7 0.6 s t hd;dat data hold time 0 0 ns t vd;ack data valid acknowledge 0.6 0.6 s t vd;dat scl low to data out valid 0.6 0.6 ns t su;dat data setup time 250 150 ns t low clock low period 4.7 1.3 s t high clock high period 4.0 0.6 s t f clock/data fall time 300 300 ns t r clock/data rise time 1000 300 ns t sp pulse width of spikes tolerance 0.5 0.5 s t d1 i 2 c-bus gpio output valid 0.2 0.2 s t d2 i 2 c-bus modem input interrupt valid 0.2 0.2 s t d3 i 2 c-bus modem input interrupt clear 0.2 0.2 s t d4 i 2 c input pin interrupt valid 0.2 0.2 s t d5 i 2 c input pin interrupt clear 0.2 0.2 s t d6 i 2 c-bus receive interrupt valid 0.2 0.2 s t d7 i 2 c-bus receive interrupt clear 0.2 0.2 s t d8 i 2 c-bus transmit interrupt clear 1.0 0.5 s t d15 scl delay after reset 3 3 s xr20m1170 43 rev. 1.1.0 i2c/spi uart with 64-byte fifo
f igure 21. scl d elay a fter r eset t d15 reset# scl f igure 22. i c-b us t iming d iagram start condition (s) bit 7 msb (a7) bit 6 (a6) protocol t buf t r t su;sta t low t high 1/f scl t f scl t hd;sta t su;dat t hd;dat sda bit 0 lsb (r/w) acknowledge (a) stop condition (p) t vd;dat t sp t vd;ack t su;sto f igure 23. w rite t o o utput slave address w a iostate reg. a data a sda gpion t d1 xr20m1170 44 i2c/spi uart with 64-byte fifo rev. 1.1.0 2
f igure 24. m odem i nput p in i nterrupt slave address w a msr register a data a sda irq# t d3 ra slave address s modem pin t d2 f igure 25. gpio p in i nterrupt slave address w a iostate reg. a data a sda irq# t d5 ra slave address s gpion t d4 p ack from slave ack from slave ack from master xr20m1170 45 rev. 1.1.0 i2c/spi uart with 64-byte fifo
f igure 26. r eceive i nterrupt d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit next start bit t d6 rx irq# f igure 27. r eceive i nterrupt c lear slave address w a rhr a data a sda irq# t d7 ra slave address s p f igure 28. t ransmit i nterrupt c lear slave address w a thr register a data a sda irq# t d8 a data xr20m1170 46 i2c/spi uart with 64-byte fifo rev. 1.1.0
ac electrical characte ristics - spi-bus timing specifications unless otherwise noted: ta=-40 o to +85 o c, vcc=1.62 - 3.63v s ymbol p arameter l imits 10% m in m ax l imits 10% m in m ax l imits 10% m in m ax u nit c onditions f scl spi clock frequency 8 16 18 mhz t tr cs# high to so three-state time 100 100 100 ns c l = 70 pf t css cs# to scl setup time 100 100 100 ns t csh cs# to scl hold time 20 20 20 ns t do scl fall to so valid time 30 20 15 ns c l = 70 pf t ds si to scl setup time 30 20 15 ns t dh si to scl hold time 10 10 10 ns t cp scl period time 125 63 55 ns t ch + t cl t ch scl high time 62 31 27 ns t cl scl low time 62 31 27 ns t csw cs# high pulse width 200 200 200 ns t d9 spi output data valid 200 200 200 ns t d10 spi modem output data valid 200 200 200 ns t d11 spi transmit interrupt clear 200 200 200 ns t d12 spi modem input interrupt clear 200 200 200 ns t d13 spi input pin interrupt clear 200 200 200 ns t d14 spi receive interrupt clear 200 200 200 ns xr20m1170 47 rev. 1.1.0 i2c/spi uart with 64-byte fifo 1.8v 2.5v 3.3v
f igure 29. spi-b us t iming t csh t css t ds t dh t cl t ch cs# sclk si so ... ... ... ... t csh t csw t do t tr f igure 30. spi w rite mcr to dtr o utput s witch a3 a2 a1 r/w a0 0 0 x d7 d6 d5 d4 d3 d2 d1 d0 cs# sclk si gpiox t d9 xr20m1170 48 i2c/spi uart with 64-byte fifo rev. 1.1.0
f igure 31. spi w rite mcr to dtr o utput s witch a3 a2 a1 r/w a0 0 0 x d7 d6 d5 d4 d3 d2 d1 d0 cs# sclk si dtr# (gpio5) t d10 f igure 32. spi w rite thr to c lear tx int a3 a2 a1 r/w a0 0 0 x d7 d6 d5 d4 d3 d2 d1 d0 cs# sclk si gpiox td11 irq# xr20m1170 49 rev. 1.1.0 i2c/spi uart with 64-byte fifo
f igure 33. r ead msr to c lear m odem int a3 a2 a1 r/w a0 0 0 x d7 d6 d5 d4 d3 d2 d1 d0 cs# sclk si so t d12 irq# f igure 34. r ead ios tate to c lear gpio int a3 a2 a1 r/w a0 0 0 x d7 d6 d5 d4 d3 d2 d1 d0 cs# sclk si so t d13 irq# xr20m1170 50 i2c/spi uart with 64-byte fifo rev. 1.1.0
f igure 35. r ead rhr to c lear rx int a3 a2 a1 r/w a0 0 0 x d7 d6 d5 d4 d3 d2 d1 d0 cs# sclk si so t d14 irq# xr20m1170 51 rev. 1.1.0 i2c/spi uart with 64-byte fifo
package dimensions (24 pin qfn - 4 x 4 x 0.9 mm, 0.50 pitch ) note: the actual center pad is m etallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 d 0.154 0.161 3.90 4.10 d2 0.098 0.110 2.50 2.80 b 0.007 0.012 0.18 0.30 e 0.0197 bsc 0.50 bsc l 0.014 0.018 0.35 0.45 k 0.008 - 0.20 - xr20m1170 52 i2c/spi uart with 64-byte fifo rev. 1.1.0
package dimensions (16 pin qfn - 4 x 4 x 0.9 mm, 0.65 pitch ) note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.000 0.008 0.00 0.20 d 0.154 0.161 3.90 4.10 d2 0.087 0.102 2.20 2.60 b 0.010 0.014 0.25 0.35 e 0.0256 bsc 0.65 bsc l 0.018 0.026 0.45 0.65 k 0.008 - 0.20 - xr20m1170 53 rev. 1.1.0 i2c/spi uart with 64-byte fifo
package dimensions (24 pin tssop - 4.4 mm ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.047 0.80 1.20 a1 0.002 0.006 0.05 0.15 a2 0.031 0.041 0.80 1.05 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.2 d 0.303 0.311 7.70 7.90 e 0.240 0.264 6.10 6.70 e1 0.169 0.177 4.30 4.50 e 0.0256 bsc 0.65 bsc l 0.018 0.030 0.45 0.75 0 8 0 8 xr20m1170 54 i2c/spi uart with 64-byte fifo rev. 1.1.0
package dimensions (16 pin tssop - 4.4 mm ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.047 0.80 1.20 a1 0.002 0.006 0.05 0.15 a2 0.031 0.037 0.80 0.95 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.2 d 0.193 0.201 4.90 5.10 e 0.240 0.264 6.30 6.60 e1 0.169 0.177 4.30 4.50 e 0.0256 bsc 0.65 bsc l 0.018 0.030 0.45 0.75 0 8 0 8 xr20m1170 55 rev. 1.1.0 i2c/spi uart with 64-byte fifo
revision history d ate r evision d escription september 2006 p1.0.0 preliminary datasheet. october 2006 p1.0.1 updated thermal resistance data. december 2006 p1.0.2 added i2c/spi timing diagrams. may 2007 1.0.0 final datasheet. updated power supply and sleep currents. updated qfn package drawing and added the parameter "k". june 2011 1.0.1 removed ?dma mode? since this is a legacy feature that is not supported in this device. added and updated maximum spi clock frequency to the ac electrical char - acteristics table for spi-bus timing. updated ordering information and removed ref - erences to the discontinued 28-pin qfn package (pdn_11-0502-01). july 2012 1.1.0 clarified "op2#" pin since the m1170 does not have op2# output pin. changed "ac electrical characteristics-ua rt clock" table according to the pcn12- 0614-02. 56 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2012 exar corporation datasheet july 2012. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xr20m1170 i2c/spi uart with 64-byte fifo rev. 1.1.0

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